1. Field of the Invention
This invention relates generally to a method for optimizing the layout of wiring in an Integrated Circuit (IC) or on a printed circuit board (PCB). More particularly, it relates to a method for minimizing skew relating to the simultaneous application of a common signal, e.g., a clock signal, as applied to separate elements on an IC or PCB.
2. Background of Related Art
Layout-related signal skew in an integrated circuit (IC) or on a printed circuit board (PCB) is a significant constraint to the increase of signal speeds. Signal skew relates to a time differential between when the voltage level of a common signal actually rises (or falls) to a given level at any component receiving that common signal. The greater the skew (or time differential), the longer the time delay which must be designed into the system to ensure that all the relevant components acting on the common signal have received the common signal properly.
FIG. 5 depicts in idealistic form a common signal (e.g., a clock signal) which is skewed in waveform (b) with respect to that shown in waveform (a). In actual practice, the resistance and capacitance in the wiring transmitting the signals create an `RC` time constant which requires a certain amount of time to rise (or fall) to a given level (e.g., 90% of maximum). Although this tends to round the rising and falling edges of the signal, the signal is shown as a square wave in FIG. 5 for ease of description. The effects of an RC time constant on printed circuit board wiring are well known in the art.
The square wave signal (e.g., a clock signal) shown in waveforms (a) and (b) of FIG. 5 represent a same or common signal as applied to two separate components located a distance apart on a printed circuit board. The clock signal shown in waveform (b) is skewed by an amount S from that shown in waveform (a) due to a larger RC time constant exhibited by the wiring relating to the component receiving the signal shown in waveform (b). This larger RC time constant is the result of many factors, e.g., longer wiring path to the second component from the clock source than to the first component, larger loading by the second component than by the first component, etc. Signal skewing, and in particular clock skewing, inhibits chip designs from gaining higher speeds.
Computer Aided Design (CAD) systems are often utilized to design features such as the wiring for integrated circuits and printed circuit boards. FIG. 6 shows a conventional CAD system 800 including a placement and routing module 802 for designing the wire routing for a given circuit on an IC or PCB.
The conventional placement and routing module 802 may perform any of several different techniques to reduce signal skew in the wire routing design: (1) Formation of an `H`-Tree for identical units; (2) Trunk and branch formation; and (3) Use of delay-locked loops.
(1) Formation of an `H`-Tree for Identical Units
The formation of an H-Tree wiring path relates to the formation of a distance-balanced tree from a common signal source to each of a plurality of identical units.
FIG. 7 shows the implementation of the conventional formation of an `H`-Tree technique to reduce signal skew. In particular, a signal source (e.g., a clock signal source) 100 provides a common signal along a central wiring 420. From the central wiring 420, equal outriggers 422-432 provide the common signal to respective elements 401-406. Ideally, the placement of the elements 401-406 is symmetrical with respect to the central wiring 420.
This technique is used most commonly with array processors and/or memory arrays, but is limited as to its application for general use because of its dependency on identically (or approximately identically) loading elements. Thus, this technique is not very popular in general use, e.g., because many IC and/or PCB designs are not array processors.
(2) Trunk and Branch Formation
This method is perhaps the most popular technique, particularly in the design of clock signal distribution in an IC and/or PCB. Using this technique, a large wiring (i.e., the `Trunk`) is created, from which the separate elements utilizing the signal are serviced by separate wiring paths (i.e., `Branches`) from the Trunk.
Thus, for instance, the output of a large capacity signal buffer provides the common signal to the Trunk, which is typically formed from a wide metal path which extends across the entire IC (or PCB). The signal buffer (e.g., a clock signal buffer) is typically capable of driving all elements connected electrically to the Trunk.
FIG. 8 shows the implementation of the conventional formation of Trunks and Branches technique to reduce signal skew.
In particular, a clock source 100 provides a common signal to an enlarged central wiring or trunk 520. Short connections 522-530 provide the common signal to each of a plurality of elements 501-505 disbursed about the IC or PCB. Ideally, the trunk 520 is as large as possible to reduce the amount of resistance (e.g., sheet resistance) between the clock source 100 and any of the elements 501-505.
Accordingly, in this conventional technique, branches 522-530 are formed out from the trunk 520, e.g., perpendicular to the length of the trunk 520, to service the respective separate elements 501-505. In some cases, several layers of branches may be used (e.g., forming `branches` and `twigs`) which are perpendicular to one another until the trunk 520 is brought into electrical connection with the intended element 501-505. Typically, each layer is formed perpendicular to the layer before, and is usually thinner than the layer before. This technique, though easily implemented, has the potential to cause rather than prevent significant signal skew between the closest node(s) (e.g., the connection between the trunk 520 and branch 522) and the farthest node(s) (e.g., the connection between the trunk 520 and branch 528).
(3) Use of Delay-Locked Loops
Using this technique, the insertion of delay-locked loops (DLLs) into blocked sections of the signal paths helps to synchronize the common signal as it is clocked into the separate sections.
FIG. 9 shows an implementation of the conventional use of delay-locked loops to reduce signal skew to functional blocks.
In particular, a clock source 100 provides a common signal to a central wiring 620, which carries the common signal to a limited number of DLLs 640-644 strategically located throughout the IC or PCB. Typically, the DLLs 640-644 are used to synchronize the application of a common signal to separate functional blocks, e.g., functional blocks 670-674. Each of the functional blocks 670-674 may comprise any number and variety of separate components, e.g., elements 601 and 602 in functional block 670, elements 603 and 604 in functional block 672, and elements 605-607 in functional block 674. The DLLs 640-644 use the clock source as a reference and generate a new clock for each block. The new clock will be synchronized with the original clock source, assuring the original clock source has small skews because it drives only the DLLs.
This technique is utilized most often in large scale design to reduce signal skew between separate functional blocks of a circuit. However, it has the potential to cause increased overhead. Moreover, because it is typically used only at the head-end of functional blocks, it does not prevent skewing of a common signal as between separate components within a functional block.
Unfortunately, this technique has its limits. For instance, if all elements were to implement a latched delay, the issue of skew would reassert itself with respect to the skew between the clock signals to each of the separate latches. Thus, there is a balance as between the number of latched delays to implement, and the benefit derived with respect to improved skew.
Although conventional techniques have tended to reduce skew in a common signal as applied to separate components, these techniques are either applicable to signals which are fed to identical types of components, require a large amount of area to implement, and/or relate only to functional blocks and not to separate components. There is still a need for a technique for reducing signal skew in an IC and/or PCB which is capable of reducing skew to each of the individual components, and/or which do not require a significant amount of surface area to implement.